The present invention is directed to complementary metal-oxide-semiconductor (CMOS) circuits, and more particularly to a method for reducing the characteristic tendency of such circuits to latch up.
A conventional CMOS circuit can have the general construction illustrated in FIG. 1. Basically, it comprises a PMOS transistor having a p-source 10 and a p-drain 12 formed in an n-substrate 14. In addition, a p-type well or tub 16 is provided in the substrate. An n-source 18 and an n-drain 20 are formed in the well to provide a complementary NMOS transistor. Of course, it will be appreciated that the CMOS circuit can have the opposite configuration, in which an NMOS transistor is formed in a p-substrate and a PMOS transistor is located in an n-well disposed on the substrate.
Examination of the structure depicted in FIG. 1 reveals that it inherently includes two integrated bipolar transistors. One of these is a vertical n-p-n transistor formed by the source and drain 18 and 20 of the NMOS transistor, the p-well 16 and the n-substrate 14. In addition, a lateral p-n-p transistor is provided by the p-well 16, the n-substrate 14 and the p-type source and drain regions 10 and 12. These two integrated transistors essentially constitute a four layer p-n-p-n device that can latch up and hold itself on under certain conditions.
More particularly, the flow of current in a bipolar transistor basically involves a flow of carriers in two opposite directions across a p-n junction. For example, in the vertical n-p-n transistor formed by the source 18 and drain 20, the well 16 and the substrate 14, the source 18 functions as the emitter and the well 16 functions as the base of the bipolar transistor. Under suitable forward biasing conditions electrons flow from the source 18 into the well 16 simultaneously with the flow of holes from the well 16 into the source 18. Since the p-well typically exhibits a long minority carrier lifetime, the electrons which are injected into it from the source 18 can be sustained by low p-well currents, and enter into the substrate 14 (which acts as a collector). Similarly, in the lateral p-n-p transistor, the source 10 functions as an emitter and the substrate 14 acts as a base. When suitably biased, holes are injected from the source 10 into the substrate 14 as electrons are contributed to the source from the substrate. These holes can be minority carriers which are collected by the well 16. Under appropriate conditions, this bidirectional injection of carriers across the junction of the substrate 14 and the well 16 can result in the four layer device becoming latched and holding itself on.
In the past, some attempts at reducing or eliminating the latch-up tendency involved the use of thick wells or buried layers, or the placement of a guard ring around the NMOS transistor to isolate it from the PMOS transistor. Other attempts focussed on reducing unexpected potential drops with epitaxial subtrates or providing diffusions to intercept injected carriers. However, each of these approaches is undesirable in that it requires additional space for the extra structures and therefore results in an increase in the overall size of the devices.